Nonvolatile memory circuits such as electrically erasable programmable read only memories (EEPROM) and Flash EEPROMs have been widely used for several decades in various circuit applications including computer memory, automotive applications, and video games. Many new applications, however, require the access time and packing density of previous generation nonvolatile memories in addition to low power consumption for battery powered circuits. One nonvolatile memory technology that is particularly attractive for these low power applications is the ferroelectric memory cell. A major advantage of these ferroelectric memory cells is that they require approximately three orders of magnitude less energy for write operations than previous generation floating gate memories. Furthermore, they do not require high voltage power supplies for programming and erasing charge stored on a floating gate. Thus, circuit complexity is reduced and reliability increased.
The term ferroelectric is something of a misnomer, since present ferroelectric capacitors contain no ferrous material. Typical ferroelectric capacitors include a dielectric of ferroelectric material formed between two closely-spaced conducting plates. One well-established family of ferroelectric materials known as perovskites has a general formula ABO3. This family includes Lead Zirconate Titanate (PZT) having a formula Pb(ZrxTi1-x)O3. This material is a dielectric with a desirable characteristic that a suitable electric field will displace a central atom of the lattice. This displaced central atom, either Titanium or Zirconium, remains displaced after the electric field is removed, thereby storing a net charge. Another family of ferroelectric materials is Strontium Bismuth Titanate (SBT) having a formula SbBi2Ta2O9. However, both ferroelectric materials suffer from fatigue and imprint. Fatigue is characterized by a gradual decrease in net stored charge with repeated cycling of a ferroelectric capacitor. Imprint is a tendency to prefer one state over another if the ferroelectric capacitor remains in that state for a long time.
A typical one-transistor, one-capacitor (1T1C) ferroelectric memory cell of the prior art is illustrated at FIG. 1. The ferroelectric memory cell is similar to a 1T1C dynamic random access memory (DRAM) cell except for ferroelectric capacitor 100. The ferroelectric capacitor (FeCAP) 100 is connected between plateline 110 and storage node 112. Access transistor 102 has a current path connected between bitline 108 and storage node 112. A control gate of access transistor 102 is connected to wordline 106 to control reading and writing of data to the ferroelectric memory cell. This data is stored as a polarized charge corresponding to cell voltage VCAP. Parasitic capacitance of bitline BL is represented by capacitor CBL 104.
Referring to FIG. 2, there is a hysteresis curve corresponding to the ferroelectric capacitor 100. The hysteresis curve includes net charge Q or polarization along the vertical axis and voltage along the horizontal axis. By convention, the polarity of cell voltage is defined as shown in FIG. 1. A stored “0”, therefore, is characterized by a positive voltage at the plateline terminal with respect to the access transistor terminal. A stored “1” is characterized by a negative voltage at the plateline terminal with respect to the access transistor terminal. A “0” is stored in a write operation by applying a voltage Vmax across the ferroelectric capacitor. This stores a saturation charge Qs in the ferroelectric capacitor. The ferroelectric capacitor, however, includes a linear component in parallel with a switching component. When the electric field is removed, therefore, the linear component discharges and only the residual charge Qr remains in the switching component. The stored “0” is rewritten as a “1” by applying −Vmax to the ferroelectric capacitor. This charges the linear and switching components of the ferroelectric capacitor to a saturation charge of −Qs. The stored charge reverts to −Qr when the electric field is removed. Finally, coercive points VC and −VC are minimum voltages on the hysteresis curve that will degrade a stored data state. For example, application of VC across a ferroelectric capacitor will degrade a stored “1” even though it is not sufficient to store a “0”. Thus, it is particularly important to avoid voltages near these coercive points unless the ferroelectric capacitor is being accessed.
Referring to FIG. 3, there is illustrated a typical write sequence for a ferroelectric memory cell as in FIG. 1. Initially, the bitline (BL), wordline (WL), and plateline (PL) are all low. The upper row of hysteresis curves illustrates a write “1” and the lower row represents a write “0”. Either a “1” or “0” is initially stored in each exemplary memory cell. The write “1” is performed when the bitline BL and wordline WL are high and the plateline PL is low. This places a negative voltage across the ferroelectric capacitor and charges it to −Qs. When plateline PL goes high, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to −Qr. At the end of the write cycle, both bitline BL and plateline PL go low and stored charge −Qr remains on the ferroelectric capacitor. Alternatively, the write “0” occurs when bitline BL remains low and plateline PL goes high. This places a positive voltage across the ferroelectric capacitor and charges it to Qs representing a stored “1”. When plateline PL goes low, the voltage across the ferroelectric capacitor is 0 V, and the stored charge reverts to Qr representing a stored “0”.
A step sensing read operation is illustrated at FIG. 4 for the ferroelectric memory cell at FIG. 1. The upper row of hysteresis curves illustrates a read “0”. The lower row of hysteresis curves illustrates a read “1”. Wordline WL and plateline PL are initially low. Bitlines BL are precharged low. At time t0 precharge signal PRE goes low, permitting the bitlines BL to float. At times t1 and t2 wordline WL and plateline PL go high, respectively, thereby permitting each memory cell connected to the active wordline WL and plateline PL to share charge with a respective bitline. A stored “1” will share more charge with parasitic bitline capacitance CBL and produce a greater bitline voltage than the stored “0” as shown between times t2 and t3. A reference voltage (not shown) is produced at each complementary bitline of an accessed bitline. This reference voltage is between the “1” and “0” voltages at t3. A difference voltage between either a “1” or “0” voltage and a corresponding reference voltage is applied to each respective sense amplifier. The sense amplifiers are activated at time t3 to amplify the difference voltage. When respective bitline voltages are fully amplified after time t3, the read “0” curve cell charge has increased from Qr to Qs. By way of comparison, the read “1” data state has changed from a stored “1” to a stored “0”. Thus, the read “0” operation is nondestructive, but the read “1” operation is destructive. At time t4, plateline PL goes low and applies −Vmax to the read “1” cell, thereby storing −Qs. At the same time, zero voltage is applied to the read “0” cell and charge Qr is restored. At the end of the read cycle, signal PRE goes high and precharges both bitlines BL return to zero volts or ground. The wordline goes low, thereby isolating the ferroelectric capacitor from the bitline. Thus, zero volts is applied to the read “1” cell and −Qr is restored.
Referring now to FIG. 5, a pulse sensing read operation is illustrated for a ferroelectric memory circuit. The read operation begins at time t0 when precharge signal PRE goes low, permitting the bitlines BL to float. Wordline WL and plateline PL are initially low, and bitlines BL are precharged low. At time t1, wordline WL goes high, thereby coupling a ferroelectric capacitor to a respective bitline. Then plateline PL goes high at time t2, thereby permitting each memory cell to share charge with the respective bitline. The ferroelectric memory cells share charge with their respective bitlines BL and develop respective difference voltages. Here, V1 represents a data “1” and V0 represents a data “0”. Plateline PL then goes low prior to time t3, and the common mode difference voltage goes to near zero. The difference voltage available for sensing is the difference between one of V1 and V0 at time t3 and a reference voltage (not shown) which lies approximately midway between voltages V1 and V0 at time t3. The difference voltage is amplified at time t3 by respective sense amplifiers and full bitline BL voltages are developed while the plateline PL is low. Thus, the data “1” cell is fully restored while plateline PL is low and the data “1” bitline BL is high. Subsequently, the plateline PL goes high while the data “0” bitline BL remains low. Thus, the data “0” cell is restored. The plateline PL goes low at time t4, and precharge signal PRE goes high at time t5. The high level of precharge signal PRE precharges the bitlines to ground or Vss. The wordline WL goes low at time t6, thereby isolating the ferroelectric capacitor from the bitline and completing the pulse sensing cycle.
Referring to FIG. 7, there is a schematic diagram of a ferroelectric memory circuit. Although the memory circuit includes many similar memory arrays, only a portion of the array is shown for clarity. The memory array includes memory cells arranged in rows corresponding to wordlines 702, 704 and columns 750, 752. Individual memory cells are indicated by circles at intersections of rows and columns. The memory circuit includes 16 platelines 710-718. Each plateline is coupled to receive a respective plateline signal PL0-PL15. Each plateline, for example plateline 710, is common to 32 rows of memory cells including rows common to wordlines 702-704. Each row of memory cells is selected by an active wordline signal. For example, row 704 is selected by active wordline signal WLX on wordline 704. Each column includes a bitline 708 and a complementary bitline 709 that form a bitline pair. Each bitline pair is coupled to a respective sense amplifier such as sense amplifier 730. Each sense amplifier has complementary output terminals coupled to local input/output lines LIO 746 and /LIO 748 by column select transistors 742 and 744, respectively. The column select transistors are selected by an active column select signal, for example, YSY on lead 740. Each column has a respective precharge circuit including first 724, second 726, and third 728 precharge transistors. The first and second precharge transistors respectively couple the bitline 708 and complementary bitline 709 to voltage terminal GND via lead 722 in response to an active precharge signal PRE on lead 720. A third precharge transistor couples the bitline 708 and complementary bitline 709 to each other in response to the active precharge signal PRE on lead 720.
In operation, the control and decode circuit 700 receives a chip enable signal CE, an address signal AN including N address bits, and a read/write signal WR. The control and decode circuit produces an active wordline signal WLX, an active column select signal YSY, an active plateline signal PL0, and a precharge signal PRE, from group signals WL, YS, and PL. A selected memory cell at the intersection of the addressed row and column receives or produces data on a respective bitline in response to a logical state of read/write signal WR. For example, when signal WR is high, a write operation is performed. Alternatively, when signal WR is low, a read operation is performed. For either a read or a write operation, when a plateline signal such as plateline signal PL0 710 goes active high, a small voltage is coupled to unselected wordlines such as wordline WLX+1 702 through parasitic capacitor 770. This parasitic capacitance exists between each wordline conductor and the respective plateline conductor but is only described for wordline WLX+1 702 for clarity. This capacitive coupling increases the voltage on each unselected wordline such as wordline WLX+1 702 by as much as 200 mV and increases subthreshold leakage by approximately two orders of magnitude. The low-to-high transition of plateline signal PL0 710 induces subthreshold current to flow from the storage node to the bitline. This charge loss couples as much as −13 mV to the storage node of each memory cell along wordline 702 following a subsequent high-to-low transition of plateline signal PL0 710. Moreover, the subthreshold current from bitline to storage node of the memory cells on wordline 702 when plateline signal PL0 is low is much less than when high as previously explained. This is because the drain-to-source voltage of each access transistor is much less. Thus, repeated access to rows of memory cells corresponding to plateline PL0 710 results in accumulated negative voltage of as much as −200 mV at the storage node of each memory cell on wordline 702.
Turning now to FIG. 6, there is a simplified diagram of an unselected ferroelectric memory cell such as on unselected wordline WLX+1 702 (FIG. 7) illustrating a problem with both step and pulse sensing schemes. Here, the same reference numerals are used as in the memory cell of FIG. 1 to show comparable elements of the ferroelectric memory cell. Resistor RGATE 114 represents subthreshold leakage path of access transistor 102. Diode 116 is a parasitic junction diode between storage node 112 and the memory circuit substrate. The wordline terminal 106 is unselected during a read operation. Resistor RWL 602 represents the parasitic resistance of wordline 106 between the unselected memory cell and the row decode circuit. Resistor RWL 602 preferably includes a polycrystalline silicon wordline in parallel with a metal strap as is known in the art and is generally referred to as a wordline conductor. N-channel transistor 600 is a part of the row decode circuit that is coupled to wordline 106 through parasitic resistance RWL 602. When the memory cell is unselected, row address signal RA remains high, thereby holding wordline 106 to ground. Plateline 110 is common to cells on a selected wordline (not shown) as well as cells on the unselected wordline WL 106. Plateline 110 is a plateline conductor. Thus, wordline terminal 106 may develop 200 mV during a low-to-high transition of the plateline 110, as will be explained in detail. Ferroelectric capacitor 100 stores a respective data signal and preferably has zero volts until a coercive voltage is developed across the terminals as previously explained. For the following exemplary discussion, ferroelectric capacitor 100 has approximately 30 fF capacitance.
During a read or write operation a selected wordline is driven high to approximately 2.2 V. Plateline PL 110 is driven high to approximately 1.65 V, and bitline BL 108 is driven low. The local polycrystalline silicon wordline between contacts of a corresponding metal wordline shunt has a significant resistance RWL. Due to this local resistance 602 of wordline WL 106 and the resistance of the row decode pull down transistor 600, the low-to-high transition of plateline PL 110 capacitively couples 200 mV to wordline terminal 106 through parasitic capacitor CP 770. This increase in gate voltage greatly increases subthreshold conduction of access transistor 102. Due to charge sharing with diode 116 and gate-to-source capacitance of access transistor 102, the plateline PL transition couples 1.6 V to storage node 112. Thus, storage node 112 goes from 0 V to 1.6 V. Under these conditions at high temperature, subthreshold leakage current ISUB of access transistor 102 increases from less than 1 nA when there is no coupling to wordline 106 to approximately 100 nA, or about two orders of magnitude, when 200 mV is coupled to wordline 106. This level of subthreshold leakage current through resistor RGATE 114 lasts for approximately 4 ns until the row decode pull down transistor 600 can restore wordline WL 106 to 0 V. The subthreshold current ISUB of 100 nA for 4 ns, however, represents a 13 mV decrease in storage node voltage subject to the previously described conditions. Moreover, this charge loss is cumulative. Minimal current flows from bitline BL 108 through access transistor 102 when plateline PL 110 returns to 0 V due to the small drain-to-source voltage. Subsequent memory accesses to rows of memory cells common to plateline 110 and resulting charge loss, however, may result in a negative voltage of as much as −200 mV at storage node 112. Such memory accesses would significantly degrade the data “1” level of the ferroelectric memory cell resulting in read errors. This degradation of the data “1” level introduces a bitline voltage imbalance and may even depolarize the ferroelectric capacitor.